The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements for providing a dielectric layer for use within a non-volatile memory semiconductor device.
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1a. As shown, memory cell 8 is viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and within which a source 13a and a drain 13b have been formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
On top of control gate 26 is a silicide layer 28 that acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a. 
FIG. 1b depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG. 1a). In FIG. 1b, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1b shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that is deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a-b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a-c and field oxides 14a-b. Interpoly dielectric layer 24 isolates floating gates 16a-c from the next conformal layer, which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of separately formed layers or films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer. The thickness and physical properties of interpoly dielectric layer 24 affect the data retention capabilities of memory cell 8.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of FIGS. 1a-b, places a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells. Of particular concern is the need to control the formation of the interpoly dielectric layer, which tends to be significantly thin in reduced-size semiconductor devices. The conventional fabrication processes associated with the multiple films associated with a typical ONO interpoly dielectric layer can be difficult to control, and/or often require additional processes which can lead to further difficulties in sub-quarter micron sized semiconductor devices. Thus, there is a need for improved interpoly dielectric layer arrangements, and more efficient methods for fabricating the same.
These needs and others are met by the present invention, which provides a single dielectric layer and methods for making the same. In accordance with certain aspects of the present invention, the single dielectric layer arrangement, which is continuous and free of internal interfaces, can be significantly thinner than a conventional ONO dielectric layer, while providing adequate isolation between the floating and control gates structures and/or increased data retention capabilities. Thus, the single dielectric layer and methods can be advantageously employed during the manufacturing of various reduced-size semiconductor devices.
In accordance with certain embodiments of the present invention, a semiconductor device having a single continuous dielectric layer is provided. The single continuous dielectric layer, which is free of internal interfaces, includes silicon and has a first oxygen-rich region, a nitrogen-rich region, and a second oxygen-rich region. The nitrogen-rich region is located between the first and second oxygen-rich regions. In certain embodiments, the single continuous dielectric layer is positioned between a floating gate structure and a control gate structure within a semiconductor device. For example, in certain embodiments the first oxygen-rich region is in direct physical contact with at least a portion of the floating gate structure and the second oxygen-rich region is in direct physical contact with at least a portion of the control gate structure. In accordance with other embodiments of the present invention, the percentage of nitrogen and/or oxygen within the single continuous dielectric layer varies within the; first oxygen-rich region, nitrogen-rich region and second oxygen-rich region. For example, the percentage of nitrogen and/or oxygen within the single continuous dielectric layer can be graded as a function of the thickness of the single continuous dielectric layer.
The above stated and needs and other are also met by a method for forming a single continuous dielectric layer in a semiconductor device in accordance with certain embodiments of the present invention. The method includes forming a first oxygen-rich region, forming a nitrogen-rich region, and forming a second oxygen-rich region. The nitrogen-rich region is located between the first and second oxygen-rich regions. The first oxygen-rich region, nitrogen-rich region and second oxygen-rich region are formed in-situ, which results in a single continuous dielectric layer free of internal interfaces. In certain embodiments, the method includes using at least dichlorosilane (DCS) and N2O gases to form the first oxygen-rich region 32, at least dichlorosilane and NH3 gases to form the nitrogen-rich region 34, and at least dichlorosilane and N2O gases to form the second oxygen-rich region 36. The method, in certain embodiments is advantageously conducted in-situ using deposition techniques, such as, for example thermal deposition techniques, chemical vapor deposition (CVD) techniques, plasma enhanced chemical vapor deposition (PECVD) techniques, or the like.
In accordance with other certain other embodiments, a method is provided for manufacturing a semiconductor device. The method includes forming a first gate structure over a substrate, forming, in-situ, a single interfaceless dielectric layer over the first gate structure, and forming a second gate structure over the single interfaceless dielectric layer.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.